RIVA128 datasheet(33/77 Pages) STMICROELECTRONICS

부품명	RIVA128

상세설명	RIVA 128™ 128-BIT 3D MULTIMEDIA ACCELERATOR

PDF	77 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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33 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

33/77

Figure 28.

SGRAM read to write, read latency of three

Table 7.

SGRAM I/O timing parameters

Figure 29.

SGRAM random write cycles within a page

NOTE

Covers either successive writes to the active row in a given bank or to the active rows in different banks. FBDQM is active

(low).

Figure 30.

SGRAM write to read cycle

NOTE

A read latency of 2 is shown for illustration

Symbol

Parameter

Min.

Max.

Unit

Notes

tHZ

Data out high impedance time

tDS

Write data setup time

tHZ

tDS

read

nop

read data n

nop

write

bank, col n

write data b

bank, col b

FBCLKx

TDDQM

Command

FBA[9:0]

FBD[63:0]

write

data n

data a

data x

data m

bank, col n

bank, col a

bank, col x

bank, col m

FBCLKx

Command

FBA[9:0]

FBD[63:0]

write

nop

read

nop

bank,

col n

bank,

col b

write

data n

write

data n

read

data b

FBCLKx

Command

FBA[9:0]

FBD[63:0]

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