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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST40RA 데이터시트(PDF) 90 Page - STMicroelectronics |
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ST40RA 데이터시트(HTML) 90 Page - STMicroelectronics |
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90 / 94 page  ADCS 7260755H STMicroelectronics 90/94 ST40RA B Implementation restrictions B.7 Interconnect B.7.1 Memory bridge functionality Ensure there is no traffic passing though the memory bridge when changing frequency. Semisynchronous modes of operation are not supported. B.7.2 Clock selection The alternate CLOCKGENB clock is not supported for the LMI. B.7.3 Pad drive control Programmable drive strength control is not supported for DDR operation. B.8 GPDMA B.8.1 Linked list support Decrementing transfers are not supported as part of link list transfer sequences B.8.2 2-D transfers 2-D transfers fail if the following conditions are met. 1 Source or destination length is greater than 64 bytes. 2 Real transfer unit is less then 32 bytes. 3 The expression length = n * 64 + tu is true, where: length is either SLENGTH or DLENGTH, tu the real transfer unit of the first access of the second line, n > 0. B.8.3 Protocol signals DACK and DRACK protocol signals have limited support. |
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