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ST40RA 데이터시트(PDF) 17 Page - STMicroelectronics

부품명 ST40RA
상세설명  32-bit Embedded SuperH Device
PDF  94 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ST40RA 데이터시트(HTML) 17 Page - STMicroelectronics

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5 System configuration
ST40RA
17/94
STMicroelectronics
ADCS 7260755H
5.3.3
ST40RA I/O device interrupt allocation
5.4
GPDMA channel mapping
For full details of the GPDMA controller see
ST40 System Architecture Manual Volume 1: System.
The ST40RA general purpose DMA controller channel map is shown in
Table 6.
Interrupt source
INTEVT
code
Interrupt priority
IPR
bit numbers
Priority
within IPR
setting unit
Value
Initial value
Mailbox
MAILBOX
0x1000
0 to 15
0
INTPRI04[0:3]
High to low
Reserved
Reserved
0 to 15
0
INTPRI04[27:24]
High to low
EMPI
INV_ADDR
0x1380
0 to 15
0
INTPRI04[31:28]
High to low
Reserved
Table 5: Mailbox and EMPI interrupt allocation
Request
number
Associated
device
Protocol
Comment
0
External device 0
DREQ or
DREQ/DRACK
The following pins are available for external peripherals:
DREQ[0:1],
DACK[0:1],
DRAK[0:1].
1
External device 1
DREQ or
DREQ/DRACK
2 and 3
Reserved
4
SCIF1 transmit
DREQ
This allow SCIF to memory and memory to SCIF transfer
to be supported on any DMA channel.
5
SCIF1 received
DREQ
6
SCIF2 transmit
DREQ
7
SCIF2 receive
DREQ
8
TMU
DREQ/DRACK
Typically used to trigger or pace memory transfers.
9 and 10
Reserved
11
PCI1
DREQ or
DREQ/DRACK
May be used to improve the efficiency of transfers to and
from the PCI.
12
PCI2
DREQ or
DREQ/DRACK
13
PCI3
DREQ or
DREQ/DRACK
14
PCI4
DREQ or
DREQ/DRACK
15 to 31
Reserved
Table 6: GPDMA request number allocation



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