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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST40RA 데이터시트(PDF) 21 Page - STMicroelectronics |
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ST40RA 데이터시트(HTML) 21 Page - STMicroelectronics |
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21 / 94 page  5 System configuration ST40RA 21/94 STMicroelectronics ADCS 7260755H 5.8 Memory bridge control The architecture of the SuperHyway interconnect is shown in Figure 3. Initiators are shown on the left, and targets are shown on the right of the interconnect. The bit width of the initiator and target ports are shown in the diagram. The ST40RA architecture requires seven memory bridges on clock change boundaries. Figure 3: ST40RA interconnect architecture Memory bridge number SuperHyway type Subsystem 1 T3 EMI target 2 T3 EMPI initiator 3 T1 EMI_SS target 4 T2 Reserved 5 T2 Reserved 6T3 PCI_ST_I 7T3 PCI_ST_T Table 9: Memory bridges SuperHyway Interconnect SH core EMPI PCI_ST_I LMI EMI PCI_ST_T Memory bridge Memory bridge Memory bridge Memory bridge P I PER SH_PER 32 32 32 GPDMA 32 64 32 32 32 |
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