STE100 datasheet(24/66 Pages) STMICROELECTRONICS

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Table 6. Control/Status register description

CSR14(offset = 70h), WPDR –Wake-up Pattern Data Register

Offset

0000h

Wake-up pattern 1 mask bits 31:0

0004h

Wake-up pattern 1 mask bits 63:32

0008h

Wake-up pattern 1 mask bits 95:64

000ch

Wake-up pattern 1 mask bits 127:96

0010h

CRC16 of pattern 1

Reserved

Wake-up pattern 1 offset

0014h

Wake-up pattern 2 mask bits 31:0

0018h

Wake-up pattern 2 mask bits 63:32

001ch

Wake-up pattern 2 mask bits 95:64

0020h

Wake-up pattern 2 mask bits 127:96

0024h

CRC16 of pattern 2

Reserved

Wake-up pattern 2 offset

0028h

Wake-up pattern 3 mask bits 31:0

002ch

Wake-up pattern 3 mask bits 63:32

0030h

Wake-up pattern 3 mask bits 95:64

0034h

Wake-up pattern 3 mask bits 127:96

0038h

CRC16 of pattern 3

Reserved

Wake-up pattern 3 offset

003ch

Wake-up pattern 4 mask bits 31:0

0040h

Wake-up pattern 4 mask bits 63:32

0044h

Wake-up pattern 4 mask bits 95:64

0048h

Wake-up pattern 4 mask bits 127:96

004ch

CRC16 of pattern 4

Reserved

Wake-up pattern 4 offset

0050h

Wake-up pattern 5 mask bits 31:0

0054h

Wake-up pattern 5 mask bits 63:32

0058h

Wake-up pattern 5 mask bits 95:64

005ch

Wake-up pattern 5 mask bits 127:96

0060h

CRC16 of pattern 5

Reserved

Wake-up pattern 5 offset

1. Offset value is from 0-255 (8-bit width).

2. To load the whole wake-up frame filtering information, consecutive 25 long words write operation to CSR14 should be done.

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