STE100 datasheet(47/66 Pages) STMICROELECTRONICS

47 / 66 page

47/66

STE10/100

6.3.2 Transmit pre-fetch data flow

Transmit FIFO size=2K-byte

two packets in the FIFO at the same time

meet the transmit min. back-to-back

Figure 10. Transmit data flow of pre-fetch data

6.3.3 Transmit early interrupt Scheme

Figure 11. Transmit normal interrupt and early interrupt comparison

place the 1st packet data into host memory

issue transmit demand

FIFO-to-host memory operation (1st packet)

time

Transmit enable

place the 2nd packet data into host memory

check the next

packet

check point

FIFO-to-host memory operation (2nd packet)

transmit threshold

place the 3rd packet data into host memory

1st packet is

transmitted, check

the 3rd packet

FIFO-to-host memory operation (3rd packet)

IFG

check point

1st packet

2nd packet

: handled by driver

: handled by STE10/100

Host to TX-FIFO Memory

Operation

Transmit data from FIFO to Media

Normal Interrupt after Transmit

Completed

Driver return buffer to upper layer

Early Interrupt after Host to TX-

FIFO Operation Completed

Driver return buffer to upper layer

The saved time when transmit

early interrupt is implemented

time

: handled by STE10/100

: handled by driver

STE100 데이터시트(PDF) 47 Page - STMicroelectronics

STE100 데이터시트(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

데이터시트 다운로드

링크 URL