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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STPCELITE 데이터시트(PDF) 68 Page - STMicroelectronics |
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STPCELITE 데이터시트(HTML) 68 Page - STMicroelectronics |
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68 / 87 page  DESIGN GUIDELINES 68/87 Release 1.3 - January 29, 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. The figure below describes a complete implementation of the external glue logic for DMA Request time-multiplexing and DMA Acknowledge demultiplexing. Like for the interrupt lines, this logic can be simplified when only few DMA channels are used in the application. This glue logic is not needed in Local bus mode as it does not support DMA transfers. Figure 6-11. Typical DMA multiplexing and demultiplexing 74x153 1C0 1Y 1G DRQ[0] DREQ_MUX[0] 1C1 1C2 1C3 2C0 2C1 2C2 2C3 A B 2G 2Y DREQ_MUX[1] DRQ[1] DRQ[2] DRQ[3] DRQ[4] DRQ[5] DRQ[6] DRQ[7] 74x138 Y0# A G2B DACK0# Y1# Y2# Y3# Y4# Y5# Y6# Y7# C B G2A ISA_CLK2X ISA_CLK ISA, Refresh ISA, PIO ISA, FDC ISA, PIO Slave DMAC ISA ISA ISA G1 DMA_ENC[0] DMA_ENC[1] DMA_ENC[2] DACK1# DACK2# DACK3# DACK5# DACK6# DACK7# |
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