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STPCELITE 데이터시트(PDF) 70 Page - STMicroelectronics |
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STPCELITE 데이터시트(HTML) 70 Page - STMicroelectronics |
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70 / 87 page ![]() DESIGN GUIDELINES 70/87 Release 1.3 - January 29, 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 6.3.9. JTAG INTERFACE The STPC integrates a JTAG interface for scan- chain and on-board testing. The only external device needed are the pull up resistors. Figure 6- 14 describes a typical implementation using these devices. Figure 6-14. Typical JTAG implementation STPC TCLK TDO 3V3 Connector 9 10 1 2 6 7 3 4 8 5 TMS TDI TRST 3V3 3V3 3V3 |
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