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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STPCELITE 데이터시트(PDF) 71 Page - STMicroelectronics |
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STPCELITE 데이터시트(HTML) 71 Page - STMicroelectronics |
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71 / 87 page  DESIGN GUIDELINES Release 1.3 - January 29, 2002 71/87 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 6.4. PLACE AND ROUTE RECOMMENDATIONS 6.4.1. GENERAL RECOMMENDATIONS Some STPC Interfaces run at high speed and need to be carefully routed or even shielded like: 1) Memory Interface 2) PCI bus 3) 14 MHz oscillator stage All clock signals have to be routed first and shielded for speeds of 27MHz or higher. The high speed signals follow the same constraints, as for the memory and PCI control signals. The next interfaces to be routed are Memory and PCI. All the analog noise-sensitive signals have to be routed in a separate area and hence can be routed indepedently. Figure 6-15. Shielding signals ground ring ground pad shielded signal line ground pad shielded signal lines |
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