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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD4046212RFS 데이터시트(PDF) 78 Page - Renesas Technology Corp |
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HD4046212RFS 데이터시트(HTML) 78 Page - Renesas Technology Corp |
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78 / 157 page  HD404629R Series 76 2 3 4 4 EVND Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic Read signal Edge detection logic System clock Timer read register D Timer counter D (TRDL) (TRDU) (TCDL) (TCDU) Input capture timer control Overflow Timer mode register D2 (TMD2) Data bus Clock line Signal line Edge detection control Edge detection selection register 2 (ESR2) Time mode register D1 (TMD1) ÷2 ÷4 ÷8 ÷32 ÷128 ÷512 ÷2048 øPER Figure 62 Block Diagram of Timer D (Input Capture Timer) Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) |
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