H8SX1663 datasheet(145/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 93 of 1102

REJ09B0294-0100

Section 5 Interrupt Controller

5.1

Features

• Two interrupt control modes

Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the

interrupt control register (INTCR).

• Priority can be assigned by the interrupt priority register (IPR)

IPR provides for setting interrupt priory. Eight levels can be set for each module for all

interrupts except for the interrupt requests listed below. The following seven interrupt requests

are given priority of 8, therefore they are accepted at all times.

 NMI

 Illegal instructions

 Trace

 Trap instructions

 CPU address error

 DMA address error (occurred in the DTC and DMAC)

 Sleep instruction

• Independent vector addresses

All interrupt sources are assigned independent vector addresses, making it unnecessary for the

source to be identified in the interrupt handling routine.

• Thirteen external interrupts

NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge

detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level

sensing, can be selected for

IRQ11 to IRQ0.

• DTC and DMAC control

DTC and DMAC can be activated by means of interrupts.

• CPU priority control function

The priority levels can be assigned to the CPU, DTC, and DMAC. The priority level of the

CPU can be automatically assigned on an exception generation. Priority can be given to the

CPU interrupt exception handling over that of the DTC and DMAC transfer.

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