H8SX1663 datasheet(32/1158 Pages) RENESAS

32 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxxii of lii

Figure 6.63 Read Timing Example of Row Address Output Retained for 1 Clock Cycle

(RCD1 = 0, RCD0 = 1, CAS Latency = 2) ............................................................. 261

Figure 6.64 Write Timing Example of Row Address Output Retained for 1 Clock Cycle

(RCD1 = 0, RCD0 = 1)........................................................................................... 262

Figure 6.65 Read Timing Example of Two Precharge Cycles

(TPC1 = 0, TPC0 = 1, CAS Latency = 2)............................................................... 263

Figure 6.66 Write Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1) .............. 264

Figure 6.67 Read Timing Example when CKSPE = 1 (CAS Latency = 2) ................................ 265

Figure 6.68 Write Timing Example when Write-Precharge Delay Cycle Insertion

(TRWL = 1) ............................................................................................................ 266

Figure 6.69 Control Timing Example of Byte Control by DQM in 16-Bit Access Space

(Read Access with Lowest Bit of Address = B'0)................................................... 267

Figure 6.70 Control Timing Example of Word Control by DQM in 16-Bit Access Space

(Read Access with Lowest Bit of Address = B'0, CAS Latency = 2) ..................... 268

Figure 6.71 Connection Example of DQM Byte/Word Control ................................................. 269

Figure 6.72 Longword Write Timing in 16-Bit Access Space (BE = 1, RCDM = 0)................. 270

Figure 6.73 Word Read Timing in 8-Bit Access Space

(BE = 1, RCDM = 0, CAS Latency = 2)................................................................. 271

Figure 6.74 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2) ... 273

Figure 6.75 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2) ... 274

Figure 6.76 Auto-Refresh Operation .......................................................................................... 276

Figure 6.77 Auto-Refresh Timing (TPC1 = 0, TPC0 = 1).......................................................... 277

Figure 6.78 Auto-Refresh Timing

(TPC1 = 0, TPC0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 1).................................... 278

Figure 6.79 Self-Refresh Timing

(TPC1 = 0, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) ................ 279

Figure 6.80 Timing Example when 1 Precharge Cycle Added

(TPC2 to TPC0 = H'1, TPC1 = 0, TPC0 = 0) ......................................................... 280

Figure 6.81 Timing of Setting SDRAM Mode Register............................................................. 282

Figure 6.82 Output Timing Example of

DACK when DDS = 1 (Write).................................... 283

Figure 6.83 Output Timing Example of

DACK when DDS = 1 (Read, CAS Latency = 2) ....... 284

Figure 6.84 Output Timing Example of

DACK when DDS = 0 (Write).................................... 285

Figure 6.85 Output Timing Example of

DACK when DDS = 0 (Read, CAS Latency = 2) ....... 286

Figure 6.86 Output Timing Example of

DACK when TRWL = 1 (Write)................................. 287

Figure 6.87 Output Timing Example of

DACK when CKSPE = 1 (Read, CAS Latency = 2).. 288

Figure 6.88 Output Timing Example of

DACK when DKC = 1 and DDS = 1 (Write).............. 289

Figure 6.89 Output Timing Example of

DACK when DKC = 1 and DDS = 0 (Write).............. 290

Figure 6.90 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 293

Figure 6.91 Example of Idle Cycle Operation (Write after Read) .............................................. 294

Figure 6.92 Example of Idle Cycle Operation (Read after Write).............................................. 295

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