H8SX1663 datasheet(150/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 98 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

CPUP2

CPUP1

CPUP0

R/(W)*

CPU Priority Level 2 to 0

These bits set the CPU priority level. When the

CPUPCE is set to 1, the CPU priority control function

over the DTC and DMAC becomes valid and the priority

of CPU processing is assigned in accordance with the

settings of bits CPUP2 to CPUP0.

000: Priority level 0 (lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (highest)

Note:

When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits

cannot be modified.

5.3.3

Interrupt Priority Registers A to I, K, L, Q, and R

(IPRA to IPRI, IPRK, IPRL, IPRQ, and IPRR)

IPR sets priory (levels 7 to 0) for interrupts other than NMI.

Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4,

and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between

the interrupt sources and the IPR settings, see table 5.2.

Bit

Bit Name

Initial Value

R/W



IPR14

R/W

IPR13

R/W

IPR12

R/W



IPR10

R/W

IPR9

R/W

IPR8

R/W

Bit

Bit Name

Initial Value

R/W



IPR6

R/W

IPR5

R/W

IPR4

R/W



IPR2

R/W

IPR1

R/W

IPR0

R/W

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