H8SX1663 datasheet(162/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 110 of 1102

REJ09B0294-0100

Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, and P5ICR register settings,

and does not change regardless of the output setting. However, when a pin is used as an external

interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the

corresponding DDR bit to 0.

A block diagram of interrupts IRQn is shown in figure 5.2.

IRQn interrupt request

IRQnE

IRQnF

Clear signal

Edge/level

detection circuit

Input buffer

Corresponding bit

in ICR

IRQnSF, IRQnSR

IRQn input

[Legend]

n = 11 to 0

Figure 5.2 Block Diagram of Interrupts IRQn

When the IRQ sensing control in ISCR is set to a low level of signal

IRQn, the level of IRQn

should be held low until an interrupt handling starts. Then set the corresponding input signal

IRQn

to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed

when the corresponding input signal

IRQn is set to high before the interrupt handling begins.

5.4.2

Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:

• For each on-chip peripheral module there are flags that indicate the interrupt request status,

and enable bits that enable or disable these interrupts. They can be controlled independently.

When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.

• The interrupt priority can be set by means of IPR.

• The DTC and DMAC can be activated by a TPU, SCI, or other interrupt request.

• The priority levels of DTC and DMAC activation can be controlled by the DTC and DMAC

priority control functions.

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