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H8SX1663 데이터시트(PDF) 254 Page - Renesas Technology Corp

부품명 H8SX1663
상세설명  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 202 of 1102
REJ09B0294-0100
6.6.6
Extension of Chip Select (
CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and
CS signals and
strobe signals such as
RD, LHWR, and LLWR.
Settings can be made in CSACR to insert cycles in which only the
CS, AS, and address signals are
asserted before and after a basic bus space access cycle. Extension of the
CS assertion period can
be set in area units. With the
CS assertion extension period in write access, the data setup and hold
times are less stringent since the write data is output to the data bus.
Figure 6.23 shows an example of the timing when the
CS assertion period is extended in basic bus
3-state access space.
Both extension cycle Th inserted before the basic bus cycle and extension cycle Tt inserted after
the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the Th cycle with the upper eight bits (CSXH7 to CSXH0) in
CSACR, and for the Tt cycle with the lower eight bits (CSXT7 to CSXT0).



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