SH7052 datasheet(339/919 Pages) RENESAS

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The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and

software standby mode.

General Registers 3A to 3D, 4A to 4D, and 5A to 5D

(GR3A to GR3D, GR4A to GR4D, and GR5A to GR5D)

Bit:

Initial value:

R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

These GR registers are 16-bit readable/writable registers with both input capture and output

compare functions. Function switching is performed by means of the timer I/O control registers

(TIOR).

When a general register is used for input capture, it stores the corresponding TCNT value on

detection of an input capture signal from an external source. The corresponding IMF bit in TSR is

set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding

TIOR. GR3A to GR3D can also be used for input capture with a channel 9 compare-match as the

trigger. In this case, the corresponding IMF bit in TSR is not set.

When a general register is used for output compare, the GR value and free-running counter

(TCNT) value are constantly compared, and when both values match, the IMF bit in the timer

status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR.

The GR registers can only be accessed by a word read or write.

The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and

software standby mode.

General Registers 9A to 9F (GR9A to GR9F)

Bit:

Initial value:

R/W:

R/W

These GR registers are 8-bit readable/writable registers with a compare-match function.

The GR value and event counter (ECNT) value are constantly compared, and when both values

match a compare-match signal is generated and the next edge is input, the corresponding CMF bit

in TSR is set to 1.

SH7052 데이터시트(PDF) 339 Page - Renesas Technology Corp