전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SH7052 데이터시트(PDF) 369 Page - Renesas Technology Corp

부품명 SH7052
상세설명  SuperHTM RISC engine
PDF  919 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 데이터시트(HTML) 369 Page - Renesas Technology Corp

Back Button SH7052 Datasheet HTML 365Page - Renesas Technology Corp SH7052 Datasheet HTML 366Page - Renesas Technology Corp SH7052 Datasheet HTML 367Page - Renesas Technology Corp SH7052 Datasheet HTML 368Page - Renesas Technology Corp SH7052 Datasheet HTML 369Page - Renesas Technology Corp SH7052 Datasheet HTML 370Page - Renesas Technology Corp SH7052 Datasheet HTML 371Page - Renesas Technology Corp SH7052 Datasheet HTML 372Page - Renesas Technology Corp SH7052 Datasheet HTML 373Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 369 / 919 page
background image
343
An example of input capture operation is shown in figure 10.16.
In the example in figure 10.16, channel 1 is activated, and input capture operation is performed
with both-edge detection specified for TIO1A, rising-edge detection for TIO1B, and falling-edge
detection for TIO1C.
Pø
TCNT1
Clock
TCNT1
TIO1A–1C
GR1A
GR1B
GR1C
TSR1
IMF1A
TSR1
IMF1B
TSR1
IMF1C
567A
567A
0003
Cleared by software
Cleared by software
567E
567D
567C
567B
567A
5679
5678
0005
0004
0003
0003
0003
0002
0001
0000
Figure 10.16 Input Capture Operation
10.3.5
One-Shot Pulse Function
Channel 8 has sixteen down-counters (DCNT8A to DCNT8P) and corresponding external pins
(TO8A to TO8P) which can be used as one-shot pulse output pins.
When a value is set beforehand in DCNT and the corresponding bit in the down-counter start
register (DSTR) is set, DCNT starts counting down, and at the same time 1 is output from the
corresponding external pin. When DCNT reaches H'0000 the down-count stops, the corresponding
bit in the timer status register (TSR) is set, and 0 is output from the external pin. The
corresponding bit in DSTR is cleared automatically. By making the appropriate setting in the
interrupt enable register (TIER), an interrupt request can be sent to the CPU.
An example of one-shot pulse operation is shown in figure 10.17.
In the example in figure 10.17, H'0005 is set in DCNT and a down-count is started.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com