SH7052 datasheet(137/919 Pages) RENESAS

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111

7.4.2

Break on CPU Data Access Cycle

1. Register settings:

UBARH = H'0012

UBARL = H'3456

UBBR = H'006A

UBCR = H'0000

Conditions set:

Address: H'00123456

Bus cycle: CPU, data access, write, word

Interrupt requests enabled

A user break interrupt occurs when word data is written into address H'00123456.

2. Register settings:

UBARH = H'00A8

UBARL = H'0391

UBBR = H'0066

UBCR = H'0000

Conditions set:

Address: H'00A80391

Bus cycle: CPU, data access, read, word

Interrupt requests enabled

A user break interrupt does not occur because the word access was performed on an even

address.

7.4.3

Break on DMA Cycle

1. Register settings:

UBARH = H'0076

UBARL = H'BCDC

UBBR = H'00A7

UBCR = H'0000

Conditions set:

Address: H'0076BCDC

Bus cycle: DMA, data access, read, longword

Interrupt requests enabled

A user break interrupt occurs when longword data is read from address H'0076BCDC.

2. Register settings:

UBARH = H'0023

UBARL = H'45C8

UBBR = H'0094

UBCR = H'0000

Conditions set:

Address: H'002345C8

Bus cycle: DMA, instruction fetch, read

(operand size not included in conditions)

Interrupt requests enabled

A user break interrupt does not occur because no instruction fetch is performed in the DMA

cycle.

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