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SH7052 데이터시트(PDF) 166 Page - Renesas Technology Corp

부품명 SH7052
상세설명  SuperHTM RISC engine
PDF  919 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 데이터시트(HTML) 166 Page - Renesas Technology Corp

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140
• Selectable bus modes: Cycle-steal mode or burst mode
• Fixed DMAC channel priority ranking
• CPU can be interrupted when the specified number of data transfers are complete.
9.1.2
Block Diagram
Figure 9.1 is a block diagram of the DMAC.
On-chip ROM
On-chip RAM
HCAN
Circuit
control
SARn
DMAC module
Register
control
Activation
control
Request
priority
control
Bus interface
Bus state
controller
On-chip
peripheral
module
DARn
DMATCRn
CHCRn
DMAOR
ATU-II
SCI0 to SCI4
A/D converter 0, 1
DEIn
External
ROM
External
RAM
External I/O
(memory
mapped)
SARn:
DARn:
DMATCRn:
CHCRn:
DMAOR:
n:
DMAC source address register
DMAC destination address register
DMAC transfer count register
DMAC channel control register
DMAC operation register
0, 1, 2, 3
Figure 9.1 DMAC Block Diagram



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