SH7052 datasheet(167/919 Pages) RENESAS

167 / 919 page

141

9.1.3

Table 9.1 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel

has four registers, and one overall DMAC control register is shared by all channels.

Table 9.1

DMAC Registers

Channel Name

Abbr.

R/W

Initial

Value

Address

Size

Access

Size

DMA source

address register 0

SAR0

R/W

Undefined

H'FFFFECC0 32 bits

16, 32*

DMA destination

address register 0

DAR0

R/W

Undefined

H'FFFFECC4 32 bits

16, 32*

DMA transfer

count register 0

DMATCR0 R/W

Undefined

H'FFFFECC8 32 bits

16, 32*

DMA channel

control register 0

CHCR0

R/W*

H'00000000 H'FFFFECCC 32 bits

16, 32*

DMA source

address register 1

SAR1

R/W

Undefined

H'FFFFECD0 32 bits

16, 32*

DMA destination

address register 1

DAR1

R/W

Undefined

H'FFFFECD4 32 bits

16, 32*

DMA transfer

count register 1

DMATCR1 R/W

Undefined

H'FFFFECD8 32 bits

16, 32*

DMA channel

control register 1

CHCR1

R/W*

H'00000000 H'FFFFECDC 32 bits

16, 32*

DMA source

address register 2

SAR2

R/W

Undefined

H'FFFFECE0 32 bits

16, 32*

DMA destination

address register 2

DAR2

R/W

Undefined

H'FFFFECE4 32 bits

16, 32*

DMA transfer

count register 2

DMATCR2 R/W

Undefined

H'FFFFECE8 32 bits

16, 32*

DMA channel

control register 2

CHCR2

R/W*

H'00000000 H'FFFFECEC 32 bits

16, 32*

SH7052 데이터시트(PDF) 167 Page - Renesas Technology Corp

SH7052 데이터시트(HTML) 167 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL