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SH7052 데이터시트(PDF) 331 Page - Renesas Technology Corp

부품명 SH7052
상세설명  SuperHTM RISC engine
PDF  919 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
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SH7052 데이터시트(HTML) 331 Page - Renesas Technology Corp

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305
10.2.14
Reload Enable Register (RLDENR)
The reload enable register (RLDENR) is an 8-bit register. The ATU-II has one RLDENR register
in channel 8.
Bit:
7
6
5
4
3
2
1
0
RLDEN
——
——
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R
R
R
R
R
R
R
RLDENR is an 8-bit readable/writable register that enables or disables loading of the reload
register8 (RLDR8) value into the down-counters (DCNT8I to DCNT8P). Loading is performed on
generation of a channel 2 compare-match signal one-shot pulse start trigger. Reloading is not
performed if there is no linkage with channel 2 (one-shot pulse function), or while the down-
counter (DCNT8I to DCNT8P) is running.
RLDENR is initialized to H'00 by a power-on reset and in hardware standby mode and software
standby mode.
• Bit 7—Reload Enable (RLDEN): Enables or disables loading of the RLDR value into DCNT8I
to DCNT8P.
Bit 7: RLDEN
Description
0
Loading of reload register value into down-counters is disabled (Initial value)
1
Loading of reload register value into down-counters is enabled
• Bits 6 to 0—Reserved: These bits always read 0. The write value should always be 0.



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