 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
7721 데이터시트(PDF) 229 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
7721 데이터시트(HTML) 229 Page - Renesas Technology Corp |
|
|
229 / 577 page  SERIAL I/O 7721 Group User’s Manual 11–26 11.3 Clock synchronous serial I/O mode Fig. 11.3.9 Processing after receive completion [When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. UARTi receive interrupt Processing after reading out receive data UART0 receive buffer register (Address 3616) UART1 receive buffer register (Address 3E16) b7 b0 Reading of receive data Receive data is read out from here. b7 b0 Checking completion of reception 1 1 Note : This figure shows the bits and registers required for processing. Refer to “Figure 11.3.12” for the change of flag state and the occurrence timing of an interrupt request. b7 b0 Checking error 1 1 Overrun error flag 0: No overrun error 1: Overrun error detected UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Receive complete flag 0: Reception not completed 1: Reception completed |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
