7721 datasheet(231/577 Pages) RENESAS

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SERIAL I/O

7721 Group User’s Manual

11–28

11.3 Clock synchronous serial I/O mode

Fig. 11.3.11 Receive operation

Fig. 11.3.12 Example of receive timing (when selecting external clock)

UARTi receive register

Receive data

MSB

LSB

Transfer clock

UARTi receive buffer register

•

D2 D3

D4 D5 D6

D1 D2

1/fEXT

RTSi

CLKi

RxDi

: When the CLKi pin’s input level is “H,” satisfy the

following conditions:

q Transmit enable bit

→ “1”

q Receive enable bit

→ “1”

q Writing of dummy data to UARTi transmit

buffer register

Receive enable bit

Transmit enable bit

Transmit buffer

empty flag

Dummy data is set to UARTi transmit buffer register.

UARTi transmit register¨

← UARTi transmit buffer register

Received data taken in

UARTi receive register

→ UARTi receive buffer register

UARTi receive buffer register is read out.

Receive complete flag

UARTi receive

interrupt request bit

The above timing diagram applies when the following

setting conditions are satisfied:

Cleared to “0” when interrupt request is accepted or

cleared by software.

q External clock selected

q RTS function selected

fEXT: Frequency of external clock

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