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7721 데이터시트(PDF) 243 Page - Renesas Technology Corp

부품명 7721
상세설명  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  577 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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SERIAL I/O
7721 Group User’s Manual
11–40
11.4 Clock asynchronous serial I/O (UART) mode
The above timing diagram applies when
the following conditions are satisfied:
q Parity disabled
q 2 stop bits
q CTS function disabled
D0 D1
D2 D3 D4 D5 D6 D7
ST
D8
D0 D1
D2 D3 D4 D5 D6 D7
ST
SP
D0 D1
ST
D8
SP
SP SP
Tc
TENDi
TxDi
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from the external.)
Tc = 16(n + 1)/fi or 16(n + 1)/fEXT
fi: BRGi count source frequency (f2, f16, f64, f512)
fEXT: BRGi count source frequency (external clock)
n: Value set in BRGi
Transfer clock
Transmit enable bit
Transmit buffer
empty flag
Transmit register
empty flag
UARTi transmit
interrupt request bit
Data is set in UARTi transmit buffer register.
Start bit
Cleared to “0” when interrupt request is accepted or cleared by software.
UARTi transmit register
UARTi transmit buffer register
Stopped because transmit enable bit = “0”
Stop bit Stop bit
Fig. 11.4.8 Example of transmit timing when transfer data length = 9 bits (when parity disabled,
____
selecting 2 stop bits, not selecting CTS function)



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