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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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7721 데이터시트(PDF) 301 Page - Renesas Technology Corp |
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7721 데이터시트(HTML) 301 Page - Renesas Technology Corp |
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301 / 577 page  7721 Group User’s Manual 13-22 DMA CONTROLLER 13.3 Control q Priority level: Fixed priority Bus request sampling DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority level : 0 > 1 > 2 > 3 DMA transfer execution channel 12 0 1 3 (Nothing) 02 1 1 03 12 3 1 3 0 2 3 1 33 q Priority level: Rotating priority Bus request sampling DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority level DMA transfer execution channel (Nothing) The above timing diagram applies on the following conditions: • No DRAM refresh request, no Hold request • All of DMAi enable bits are “1.” Fig. 13.3.1 Example of determining channel priority levels |
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