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7721 Group User’s Manual

13-27

DMA CONTROLLER

13.3 Control

(2)

Forced termination

The methods of terminating DMAC other than normal termination are as follows:

___

• Drives the TC pin’s input level from “H” to “L” during a DMA transfer (when the TC pin is valid).

• Writes “0” to the DMAi enable bit.

Table 13.3.5 lists the states of DMAC at forced termination.

Table 13.3.5 States of DMAC at forced termination

Item

State

DMAi interrupt request bit

DMAi request bit

DMAi enable bit

___

output

Channel priority levels

Not changed.

___

When the TC pin is used for forced termination, select “TC pin valid” (bit 1 at address 6816 = “1”).

___

Forced termination by the TC input is valid in the following cases:

• During a DMA transfer in the burst transfer mode (edge sense)

• During the term from the DMA transfer start until the transfer completion of an entire batch of

data in the burst transfer mode with the level sense selected. (It is also valid while the CPU has

the right to use bus).

___

• During a DMA transfer in the cycle-steal transfer mode (Forced termination by the TC input is

invalid while the CPU has the right to use bus.)

___

The TC pin’s input is determined at the falling edge of

φ1, and DMAC will relinquish the right to use

bus to the CPU upon completion of the 1-unit transfer under execution at that time.

At the forced termination by the DMAi enable bit, “0” is written to this bit at the rising edge of E of

a write cycle to the DMAi enable bit. Accordingly, DMAi is disabled after this write.

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