7721 datasheet(313/577 Pages) RENESAS

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7721 Group User’s Manual

13-34

DMA CONTROLLER

13.4 Operation

(3)

Address directions in 2-bus cycle transfer

In 2-bus cycle transfer, the address direction of a transfer source and that of a transfer destination

each can be selected independently. (Refer to “Figure 13.2.6.”) Addresses move in the specified

direction by the transfer unit. Tables 13.4.2 through 13.4.4 list address directions in 2-bus cycle

transfer and examples of transfer result.

Tables 13.4.2 Address directions in 2-bus cycle transfer and examples of transfer result (1)

High order

Transfer unit : 8 bits

Address direction

Transfer

source

Fixed

Forward

Backward

Transfer unit : 16 bits

Transfer

sequence

Data

External data bus width : 16 bits or 8 bits

Transfer

destination

Fixed

Data arrangement

on transfer source

memory

Data arrangement

on transfer source

memory

Data arrangement on

transfer destination

memory (transfer result)

Transfer

sequence

Data arrangement on

transfer destination

memory (transfer result)

Data

Low order

Data

Low order

High order

Data

Low order

Data

Low order

High order

Data

Low order

High order

Data

Low order

High order

Data

Low order

Data

Low order

High order

Data

Low order

High order

Data

Low order

High order V

Data

V : Transfer start address

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