7733 datasheet(458/940 Pages) RENESAS

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APPLICATIONS

7733 Group User’s Manual

17–51

(3) Approximate flowchart

Fig. 17.4.5 Approximate flowchart (1)

[F_WIT]: Flag used to determine whether an INT0 interrupt

request has occurred or not

Main clock oscillation circuit: Oscillating

<<C>>

Main routine

System clock selection bit

“1”

(bit 3 at address 6C 16)

System clock:

Main clock

Sub clock

<<A>>

VREF connection selection bit

“1”

(bit 5 at address 1F 16)

Pin VREF is disconnected from resistor ladder network.

(Note 1)

Port level is fixed.

(Note 2)

Wait mode is selected.

Main clock stop bit

“1”

(bit 2 at address 6C 16)

Main clock oscillation circuit: Stopped

<<B>>

Main clock stop bit

“0”

(bit 2 at address 6C 16)

0: INT0 interrupt

[F_WIT]

“1”

Clock timer

interrupt request

occurs.

[F_WIT] = “1” ?

“1”: Clock timer

interrupt

WIT

INT0

interrupt

request occurs.

(By this setting, the wait mode is terminated

only when an INT0 interrupt request occurs.)

Bits 2 to 0 at addresses 70 16

to 7B16, 7E16, and 7F16

“0002”

Interrupts other than timer B2 and INT0 interrupts are

disabled.

Timer B2 count start flag

“1”

(bit 7 at address 40 16)

Clock timer starts counting .

System clock selection bit

“0”

(bit 3 at address 6C 16)

System clock:

Sub clock

Main clock (Note 3)

<<D>>

<<A>> <<B>> <<C>> <<D>>: Refer to Figure 17.4.8.

For Notes 1 to 3, refer to the next page.

17.4 Power saving

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