7733 datasheet(134/940 Pages) RENESAS

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TIMER A

7733 Group User’s Manual

6–23

6.4.1 Setting for event counter mode

Figure 6.4.3 and 6.4.4 show an initial setting example for registers related to the event counter mode.

Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4.

INTERRUPTS.”

6.4 Event counter mode

Fig. 6.4.3 Initial setting example for registers related to event counter mode (1)

g Counter divides the count source frequency by (n + 1)

while counting down or by (FFFF16 – n + 1) while counting

up.

Setting of the up-down flag

Timer A0 up-down flag

Continued to

“Initial setting example for registers related to event counter mode (2)”

on the next page

Two-phase pulse signal processing type selection bit

(Valid only for i = 3)

0: Normal processing

1: Quadruple processing

Selection of the event counter mode and each function

Timer Ai mode register (i = 0 to 4)

(addresses 5616 to 5A16)

Pulse output function selection bit

0: No pulse is output.

1: Pulse is output.

Count polarity selection bit

0: Counts at falling edge of external signal.

1: Counts at rising edge of external signal.

Up-down switching factor selection bit

0: Contents of the up-down flag

1: Input signal to pin TAiOUT

Count type selection bit

(Valid only for i = 2 to 4)

0: Reload count type

1: Free-run count type

Event counter mode is selected.

Setting of the division ratio

Values 000016 to FFFF16 (n) can be set.

(b15)

(b8)

Timer A0 register (addresses 4716, 4616)

Timer A1 register (addresses 4916, 4816)

Timer A2 register (addresses 4B16, 4A16)

Timer A3 register (addresses 4D16, 4C16)

Timer A4 register (addresses 4F16, 4E16)

Up-down flag (address 4416)

•When up-down flag is selected as up-down switching

factor, set corresponding up-down flag.

0: Countdown

1: Countup

•Selection of the two-phase pulse signal processing function

Set the corresponding bit to “1.”

0: Two-phase pulse signal processing function is disabled.

1: Two-phase pulse signal processing function is enabled.

Timer A1 up-down flag

Timer A2 up-down flag

Timer A3 up-down flag

Timer A4 up-down flag

Timer A2 two-phase pulse signal

processing selection bit

Timer A3 two-phase pulse signal

processing selection bit

Timer A4 two-phase pulse signal

processing selection bit

7733 데이터시트(PDF) 134 Page - Renesas Technology Corp

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