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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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7733 데이터시트(PDF) 201 Page - Renesas Technology Corp |
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7733 데이터시트(HTML) 201 Page - Renesas Technology Corp |
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201 / 940 page  TIMER B 7733 Group User’s Manual 7–38 7.6 Clock timer 7.6.2 Operation of clock timer When the count start flag is set to “1,” the counter starts counting of the count source. When an underflow occurs, the reload register’s contents is reloaded, and then counting is continued. The timer B2 interrupt request bit is set to “1” when the underflow occurs in . After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. For example, if f(XCIN) = 32.768 kHz, a timer B2 interrupt request can be issued every second when value “3FF16” is set into the timer B2 register (addresses 5416 and 5516) and every minute when value “EFFF16” is set into the register. Figure 7.6.4 shows an operation example of clock timer. Fig. 7.6.4 Operation example of clock timer FFFF16 n 000016 Count start flag Timer B1 interrupt request bit “1” “1” Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software “0” “0” 000016 FFFF16 n Cleared to “0” by software |
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