7733 datasheet(214/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–11

(1) Transmit enable bit (bit 0)

When this bit is set to “1,” UARTi enters the transmit enable state.

When this bit is cleared to “0” during transmission, UARTi enters the transmit disable state after the

transmission which is in progress at this clearing is completed.

(2) Transmission buffer empty flag (bit 1)

This flag is set to “1” when data is transferred from the UARTi transmission buffer register to the

UARTi transmission register.

This flag is cleared to “0” when data is set to the UARTi transmission buffer register.

(3) Receive enable bit (bit 2)

When this bit is set to “1,” UARTi enters the receive enable state.

When this bit is cleared to “0” during reception, UARTi quits the reception immediately and enters the

receive disable state.

(4) Receive completion flag (bit 3)

This flag is set to “1” in the following case;

• when data is ready in the UARTi receive register and is transferred to the UARTi receive buffer

This flag is cleared to “0” in one of the following cases;

• when the low-order byte of the UARTi receive buffer register is read out,

• when the receive enable bit (bit 2) is cleared to “0,”

• when port P8 is used as a programmable I/O port by clearing the serial I/O mode selection bits (bits

2 to 0 at addresses 3016, 3816 and 6416) to “0002”

8.2 Block description

7733 데이터시트(PDF) 214 Page - Renesas Technology Corp