7733 datasheet(218/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–15

8.2.6 UARTi receive register and UARTi receive buffer register

Figure 8.2.10 shows the block diagram for the receiver. Figure 8.2.11 shows the structure of the UARTi

receive buffer register.

Fig. 8.2.10 Block diagram for receiver

8.2 Block description

Fig. 8.2.11 Structure of UARTi receive buffer register

(b15)

(b8)

UART0 receive buffer register (addresses 37 16, 3616)

UART1 receive buffer register (addresses 3F 16, 3E16)

UART2 receive buffer register (addresses 6B 16, 6A16)

Bit

Not implemented.

A value of “0” is read out from here.

The receive data is read out from here.

At reset

Un-

defined

Functions

8 to 0

15 to 9

—

Clock sync.

PAR

2SP

1SP

UART

RxDi

SP : Stop bit

PAR : Parity bit

8-bit UART

9-bit UART

7-bit UART

9-bit UART

Clock sync.

7-bit UART

8-bit UART

Data bus (even)

Data bus (odd)

Bit converter

UARTi receive register

Parity

enabled

Parity

disabled

UARTi receive

buffer register

(Note)

Note: The bit converter is not assigned for UART2.

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