7733 datasheet(225/940 Pages) RENESAS

225 / 940 page

SERIAL I/O

7733 Group User’s Manual

8–22

8.3.1 Transfer clock (sync clock)

Data is transferred synchronously with the transfer clock. For the transfer clock, the following items can

be specified:

q Whether to generate the transfer clock internally or to input it from the external.

q Polarity of a clock which is output from the CLKi pin (UART0, UART1)

q Number of transfer clock output pins (UART0).

Note that the transfer clock is generated while the transmit control circuit is operating. Therefore, even

when performing only reception, set the transmit enable bit to “1” and make the transmit control circuit

operate by setting dummy data into the UARTi transmission buffer register.

(1) How to generate transfer clock internally

A count source is selected with the BRG count source selection bits. The count source is divided in

the BRGi, and then the BRGi’s output is further divided by 2. (In this way, the transfer clock is

generated.) This transfer clock is output from the CLKi pin.

[Setting for related registers]

q An internal clock is selected (bit 3 at addresses 3016, 3816, and 6416 = “0”).

q The BRGi’s count source is selected (bits 1 and 0 at addresses 3416, 3C16, and 6816).

q A value of “divide value – 1” (= n: 0016 to FF16) is set into the BRGi (addresses 3116, 3916, and

6516).

Transfer clock’s frequency =

fi: BRGi’s count source frequency (f2, f16, f64, and f512)

q Transmission is enabled (bit 0 at addresses 3516, 3D16, and 6916 = “1”).

q Data is set into the UARTi transmission buffer register (addresses 3216, 3A16, and 6616)

[Pin status]

q Transfer clock is output from the CLKi pin.

q Serial data is output from the TxDi pin. (Dummy data is output when only reception is performed.)

(2) How to input transfer clock from the external

A clock which is input from the CLKi pin is the transfer clock.

[Setting related registers]

q An external clock is selected (bit 3 at addresses 3016, 3816, and 6416 = “1”).

q Transmission is enabled (bit 0 at addresses 3516, 3D16, and 6916 = “1”).

q Data is set into the UARTi transmission buffer register (addresses 3216, 3A16, 6616).

[Pin status]

q Transfer clock is input from the CLKi pin.

q Serial data is output from the TxDi pin. (Dummy data is output when only reception is performed.)

2 (n+1)

8.3 Clock synchronous serial I/O mode

7733 데이터시트(PDF) 225 Page - Renesas Technology Corp