7733 datasheet(224/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–21

____

Note: The RTS function is not assigned for UART2.

Table 8.3.2 Functions of I/O pins in clock synchronous serial I/O mode

8.3 Clock synchronous serial I/O mode

Table 8.3.1 lists the performance overview in the clock synchronous serial I/O mode and Table 8.3.2 lists

the functions of I/O pins in this mode.

Table 8.3.1 Performance overview in clock synchronous serial I/O mode

Item

Transfer data format

Transfer rate

Transmit/Receive control

Functions

Transfer data has a length of 8 bits.

LSB first or MSB first is selected by software.

BRGi’s output divided by 2

Maximum of 5 Mbps

____

CTS

function or RTS function is selected by software (Note).

When internal clock is selected

When external clock is selected

Pin name

TxDi

(P83, P87, P75)

RxDi

(P82, P86, P74)

CLKi

(P81, P85, P73)

_________ _________

CTS0

/RTS0 (P80),

_________ _________

CTS1

/RTS1 (P84)

(Note 1)

_________

CTS2

(P72)

Functions

Serial data output

Serial data input

Transfer clock output

Transfer clock input

____

CTS

input

____

RTS

output

Programmable I/O port

____

CTS

input

Programmable I/O port

Method of selection

(They output dummy data when only reception is performed.)

Ports P7 and P8 direction registers’ corresponding bits =“0”

(They can be used as input ports when only transmission is

performed.)

Internal/External clock selection bit = “0”

Internal/External clock selection bit = “1”

____ ____

CTS

/RTS enable bit = “0”

____ ____

CTS

/RTS function selection bit = “0”

____ ____

CTS

/RTS enable bit = “0”

____ ____

CTS

/RTS function selection bit = “1”

____ ____

CTS

/RTS enable bit = “1”

____

CTS

enable bit = “0”

____

CTS

enable bit = “1”

Port P7 direction register: Address 1116

Port P8 direction register: Address 1416

Internal/External clock selection bit: Bit 3 at addresses 3016, 3816, and 6416

____ ____

CTS

/RTS enable bit: Bit 4 at addresses 3416 and 3C16

____ ____

CTS

/RTS function selection bit: Bit 2 at addresses 3416 and 3C16

____

CTS

enable bit: Bit 2 at address 6816

g The TxDi pin outputs “H” level from when a UARTi’s operating mode is selected until transfer starts.

(The TxDi pin is in a floating state when N-channel open-drain output is selected.)

g In UART0, multiple transfer clock output pins can be used. (Refer to Table 8.3.3.)

____

Notes 1: The RTS function is not assigned for UART2.

2: As for CLKS0 and CLKS1, refer to section “8.3.1 (4) Number of transfer clock output pins

(UART0).”

8.3 Clock synchronous serial I/O mode

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