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STOP AND WAIT MODES

7733 Group User’s Manual

11–12

11.3.4 Stop mode terminating operation by hardware reset

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When terminating the stop mode by hardware reset, input “L” level to pin RESET from the external circuit

until oscillation of an oscillator which is connected to the main-clock oscillation circuit is stabilized.

The CPU and SFR area are initialized in the same way as at system reset. However, the internal RAM area

retains the same contents as that before the STP instruction was executed. The terminating sequence is

the same as the internal processing sequence after reset.

When determining whether hardware reset was applied for termination of the stop mode or system reset

was applied, use software after reset.

For reset, refer to chapter “13. RESET.”

11.3.5 Precautions for stop mode

1. In the mask ROM version, select “STP instruction enabled” with “STP instruction option” on “MASK ROM

ORDER CONFIRMATION FORM.” (In the built-in PROM and external ROM versions, STP instruction is

always enabled.)

2. “Stop mode terminating operation by an interrupt request occurrence (when not using watchdog timer)”

can be selected only when an external clock is stably input to a clock input pin for a clock which is

selected as the system clock.

In one of the following cases, select “Stop mode terminating operation by an interrupt request occur-

rence (when using watchdog timer)”:

q When an oscillator is connected between input and output pins for a clock which is selected as the

system clock

q When there is a possibility that the above external clock is temporarily unstable in termination of the

stop mode

11.3 Stop mode

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