TMS320VC5421 datasheet(35/88 Pages) TI

35 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

DMA accesses to external memory (continued)

These new bit fields were created to allow the user to define the space-select for the DMA (internal/external).

Also, a new extended destination data page (XDSTDP[6:0], subaddress 029h) and extended source data page

(XSRCDP[6:0], subaddress 028h) have been created.

DLAXS(DMMCRn[5])

Destination

0 = No external access (default internal)

Destination

1 = External access

SLAXS(DMMCRn[11])

Source

0 = No external access (default internal)

Source

1 = External access

For the CPU external access, software can configure the memory cells to reside inside or outside the program

address map. When the cells are mapped into program space, the device automatically accesses them when

their addresses are within bounds. When the program address generation (PAGEN) logic generates an address

outside its bounds, the device automatically generates an external access. All DMA I/O space accesses are

mapped to the core-to-core FIFO.

DMA controller synchronization events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit

field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event

for a channel. The list of possible events and the DSYN values are shown in Table 10.

Table 10. DMA Synchronization Events

DSYN VALUE

DMA SYNCHRONIZATION EVENT

0000b

No synchronization used

0001b

McBSP0 Receive Event

0010b

McBSP0 Transmit Event

0011b

McBSP2 Receive Event

0100b

McBSP2 Transmit Event

0101b

McBSP1 Receive Event

0110b

McBSP1 Transmit Event

0111b

FIFO Receive Buffer Not Empty Event

1000b

FIFO Transmit Buffer Not Full Event

1001b – 1111b

Reserved

DMA channel interrupt selection

The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 0, 1, 2,

and 3 are multiplexed with other interrupt sources. DMA channels 0 and 1 share an interrupt line with the receive

and transmit portions of McBSP2 (IMR/IFR bits 6 and 7), and DMA channels 2 and 3 share an interrupt line with

the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11). When the ’5421 is reset, the interrupts

from these four DMA channels are deselected. The INTSEL bit field in the DMA channel priority and enable

control (DMPREC) register can be used to select these interrupts, as shown in Table 11.

Table 11. DMA Channel Interrupt Selection

INTSEL Value

IMR/IFR[6]

IMR/IFR[7]

IMR/IFR[10]

IMR/IFR[11]

00b (reset)

BRINT2

BXINT2

BRINT1

BXINT1

01b

BRINT2

BXINT2

DMAC2

DMAC3

10b

DMAC0

DMAC1

DMAC2

DMAC3

11b

Reserved

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