TMS320VC5421 datasheet(47/88 Pages) TI

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TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts (continued)

The interprocessor interrupt (IPINT) bit of the interrupt mask register (IMR) and the interrupt flag register (IFR)

allows the subsystem to perform interrupt service routines based on the other subsystem activity. Incoming

IPINT interrupts are latched in IFR.14. Generating an interprocessor interrupt is performed by writing a “1” to

the IPIRQ field of the bank-switching control register (BSCR). Subsequent interrupts must first clear the interrupt

by writing “0” to the IPIRQ field. Figure 20 shows the bit layout of the IMR and the IFR. Table 23 describes the

bit functions.

For example, if subsystem A is required to notify subsystem B of a completed task, subsystem A must write a

“1” to the IPIRQ field to generate a IPINT interrupt on subsystem B. On subsystem B, the IPINT interrupt is

latched in IFR.14. Figure 5 shows the bit layout of the BSCR and Table 6 describes the bit functions.

Reserved

IPINT

DMAC5

DMAC4

XINT1 or

DMAC3

RINT1 or

DMAC2

HPINT

Reserved

R/W

765

43210

XINT2 or

DMAC1

RINT2 or

DMAC0

XINT0

RINT0

TINT

Reserved

INT1

INT0

R/W

LEGEND: R = Read, W = Write

Figure 20. Bit Layout of the IMR and IFR Registers for Subsystems A and B

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