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TMS320VC5421 데이터시트(PDF) 67 Page - Texas Instruments |
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TMS320VC5421 데이터시트(HTML) 67 Page - Texas Instruments |
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67 / 88 page ![]() TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 67 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HOLD and HOLDA timing switching characteristics over recommended operating conditions for memory control signals and HOLDA [H = 0.5 tc(CO)] (see Figure 35) PARAMETER MIN MAX UNIT t Valid time, HOLDA low after CLKOUT low 0 5 ns tv(HOLDA) Valid time, HOLDA high after CLKOUT low – 2 3 ns tw(HOLDA) Pulse duration, HOLDA low duration 2H–3 ns timing requirements for HOLD [H = 0.5 tc(CO)] (see Figure 35) MAX MIN UNIT tw(HOLD) Pulse duration, HOLD low duration 4H+10 ns tsu(HOLD) Setup time, HOLD low/high before CLKOUT low 10 ns HOLDA HOLD CLKOUT tv(HOLDA) tv(HOLDA) tw(HOLDA) tw(HOLD) tsu(HOLD) tsu(HOLD) Figure 35. HOLD and HOLDA Timing (HM = 1) |
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