CDCE62002 datasheet(6/49 Pages) TI

6 / 49 page

Synthesizer Block

PFD/

Prescaler

/2,/3,/4,/5

InputDivider

/1 - /256

SMART_MUX

SYNTH

70 kHz –

400 kHz

/1,/2,/5,/8,/10,/16,/20

/8 - /1280

1.75 GHz –

2.356 GHz

FeedbackDivider

FeedbackBypassDivider

AUX_IN

Output Block

/1,2,3,4,5

UxP

UxN

/1 - /8

DigitalPhase Adjust (7-bits)

SYNTH

Sync

Pulse

Enable

LVDS

ClockDividerModule 0 & 1

LVPECL

OutputBufferControl

CDCE62002

SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

Figure 5 presents a high-level overview of the Synthesizer Block on the CDCE62002. This block contains the

Phase lock loop, internal loop filter and dual Voltage controlled oscillators. Only one VCO is selected at a time.

The loop is closed after a Prescaler divider that feeds the output stage the feedback divider.

Figure 5. CDCE62002 Synthesizer Block

Both identical output blocks incorporate a Clock Divider Module (CDM), and a universal output array buffer

driver. If an individual clock output channel is not used, then the user should disable the CDM and Output Buffer

for the unused channel to save device power. Each channel includes 4-bit in register “0” to control the divide

ratio. The output divider supports divide ratios from divide by 1 (bypass the divider) 2,3,4,5,8,10,12,16,20,24 and

32.

Figure 6. CDCE62002 Output Block

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