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CDCE62002 데이터시트(PDF) 20 Page - Texas Instruments

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부품명 CDCE62002
상세설명  Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
PDF  49 Pages
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CDCE62002 SPI Command Structure
CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
The CDCE62002 supports four commands issued by the Master via the SPI:
•
Write to RAM
•
Read Command
•
Copy RAM to EEPROM – unlock
•
Copy RAM to EEPROM – lock
Table 6 provides a summary of the CDCE62002 SPI command structure. The host (master) constructs a Write to
RAM command by specifying the appropriate register address in the address field and appends this value to the
beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first. The
host must issue a Read Command to initiate a data transfer from the CDCE62002 back to the host. This
command specifies the address of the register of interest in the data field.
Table 6. CDCE62002 SPI Command Structure
Data Field (28 Bits)
Addr Field
(4 BIts)
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
Register
Operation
NVM
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
3
2
1
0
0
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
2
Status/Control
No
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
Instruction
Read Command
No
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
A
A
A
1
1
1
0
Instruction
RAM EEPROM
Unlock
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Instruction
RAM EEPROM
Lock
(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
(1)
CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration can
only be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed.
20
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