PCF8576CUSLASH2 datasheet(19/56 Pages) NXP

19 / 56 page

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

19 of 56

NXP Semiconductors

PCF8576C

Universal LCD driver for low multiplex rates

When display data is transmitted to the PCF8576C, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for an acknowledge cycle as with the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triplets or

quadruplets. To illustrate the ﬁlling order, an example of a 7-segment numeric display

showing all drive modes is given in Figure 13; the RAM ﬁlling organization depicted

applies equally to other LCD types.

The following applies to Figure 13:

• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 4-bit RAM words.

• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to

three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difﬁcult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into

row 0, 1, 2 and 3 of two successive 4-bit RAM words.

Display RAM bit map showing direct relationship between RAM addresses and segment outputs;

also between bits in a RAM word and the backplane outputs.

Fig 12. Display RAM bit map

1234

display RAM addresses (columns)/segment outputs (S)

display RAM bits

(rows)/

backplane outputs

(BP)

mbe525

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