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PCF8576CU/2 데이터시트(PDF) 36 Page - NXP Semiconductors

부품명 PCF8576CU/2
상세설명  Universal LCD driver for low multiplex rates
PDF  56 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF8576CU/2 데이터시트(HTML) 36 Page - NXP Semiconductors

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PCF8576C_9
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 09 — 9 July 2009
36 of 56
NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8576Cs. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the defining a multiplex mode when PCF8576Cs
with differing SA0 levels are cascaded).
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8576C asserts the SYNC line
and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is
restored by the first PCF8576C to assert SYNC. The timing relationship between the
backplane waveforms and the SYNC signal for the various drive modes of the PCF8576C
are shown in Figure 30.
For single plane wiring of packaged PCF8576Cs and chip-on-glass cascading, see
Figure 31.
.
Fig 29. Cascaded PCF8576C configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
1
17 to 56
13,15,
14,16
13,15,
14,16
2
3
4
6
78
512
910
11
4 backplanes
40 segment drives
LCD PANEL
(up to 2560
elements)
PCF8576CT
A0
A1
A2
SA0 VSS
VDD
VSS
VLCD
VDD
VLCD
mbe533
SDA
SCL
SYNC
CLK
OSC
15
12
2
3
4
6
17 to 56
BP0 to BP3
(open-circuit)
A0
A1
A2
SAO VSS
VDD
VLCD
PCF8576CT
BP0 to BP3
R
≤
tr
2CB
40 segment drives



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