PCF8576CUSLASH2 datasheet(26/56 Pages) NXP

26 / 56 page

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

26 of 56

NXP Semiconductors

PCF8576C

Universal LCD driver for low multiplex rates

8.3 Command decoder

The command decoder identiﬁes command bytes that arrive on the I2C-bus. All available

commands carry a continuation bit C in their most signiﬁcant bit position as shown in

Figure 19. When this bit is set, it indicates that the next byte of the transfer to arrive will

also represent a command. If this bit is reset, it indicates that the command byte is the last

in the transfer. Further bytes will be regarded as display data.

The ﬁve commands available to the PCF8576C are deﬁned in Table 8.

Fig 18. I2C-bus protocol

mbe538

011100

0 A

COMMAND

DISPLAY DATA

slave address

R/W

acknowledge by

all addressed

PCF8576Cs

acknowledge

by A0, A1 and A2

selected

PCF8576C only

≥ 1 byte(s)

≥ 0 byte(s)

1 byte

update data pointers

and if necessary,

subaddress counter

(1) C = 0; last command

(2) C = 1; commands continue

Fig 19. General format of byte command

msa833

REST OF OPCODE

MSB

LSB

Table 8.

Deﬁnition of PCF8576C commands

Command

OPCODE

Reference

Description

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

mode set

Section 8.3.1 deﬁnes LCD drive mode, LCD bias

conﬁguration, display status and power

dissipation mode

load data

pointer

Section 8.3.2 data pointer to deﬁne one of 40 display

RAM addresses

device select C

Section 8.3.3 deﬁne one of eight hardware

subaddresses

bank select

Section 8.3.4 bit I: deﬁnes input bank selection

(storage of arriving display data);

bit O: deﬁnes output bank selection

(retrieval of LCD display data)

blink

BF1

BF0

Section 8.3.5 deﬁnes the blink frequency and blink

mode

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