ATmega162 datasheet(73/324 Pages) ATMEL

73 / 324 page

2513K–AVR–07/09

ATmega162/V

• AIN1/TXD1 – Port B, Bit 3

AIN1, Analog Comparator Negative input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

TXD1, Transmit Data (Data output pin for USART1). When the USART1 Transmitter is enabled,

this pin is configured as an output regardless of the value of DDB3.

• AIN0/RXD1 – Port B, Bit 2

AIN0, Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

RXD1, Receive Data (Data input pin for USART1). When the USART1 Receiver is enabled this

pin is configured as an input regardless of the value of DDB2. When the USART1 forces this pin

to be an input, the pull-up can still be controlled by the PORTB2 bit.

• T1/OC2 – Port B, Bit 1

T1, Timer/Counter1 Counter Source.

OC2, Output Compare Match output: The PB1 pin can serve as an external output for the

Timer/Counter2 Compare Match. The PB1 pin has to be configured as an output (DDB1 set

(one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer

function.

• T0/OC0 – Port B, Bit 0

T0, Timer/Counter0 counter source.

OC0, Output Compare Match output: The PB0 pin can serve as an external output for the

Timer/Counter0 Compare Match. The PB0 pin has to be configured as an output (DDB0 set

(one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer

function.

clk

I/O, Divided System Clock: The divided system clock can be output on the PB0 pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the

PORTB0 and DDB0 settings. It will also be output during reset.

Table 33 and Table 34 relate the alternate functions of Port B to the overriding signals shown in

Figure 32 on page 68. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal,

while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

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