ATmega162 datasheet(52/324 Pages) ATMEL

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2513K–AVR–07/09

ATmega162/V

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUCSR as early as possible in the program. If the register is cleared before another

reset occurs, the source of the Reset can be found by examining the Reset Flags.

Internal Voltage

Reference

ATmega162 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator.

Voltage Reference

Enable Signals and

Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in Table 21. To save power, the reference is not always turned on. The ref-

erence is on during the following situations:

When the BOD is enabled (by programming the BODLEVEL Fuses).

When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always allow the

reference to start up before the output from the Analog Comparator is used. To reduce power

consumption in Power-down mode, the user can avoid the two conditions above to ensure that

the reference is turned off before entering Power-down mode.

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is

the typical frequency at V

CC = 5V. See characterization data for typical values at other VCC lev-

els. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted

as shown in Table 23 on page 54. The WDR – Watchdog Reset – instruction resets the Watch-

dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.

Eight different clock cycle periods can be selected to determine the reset period. If the reset

period expires without another Watchdog Reset, the ATmega162 resets and executes from the

Reset Vector. For timing details on the Watchdog Reset, refer to page 54.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3

different safety levels are selected by the Fuses M161C and WDTON as shown in Table 22.

Safety level 0 corresponds to the setting in ATmega161. There is no restriction on enabling the

Table 21. Internal Voltage Reference Characteristics

Symbol

Parameter

Min.

Typ.

Max.

Units

VBG

Bandgap reference voltage

1.05

1.10

1.15

tBG

Bandgap reference start-up time

µs

IBG

Bandgap reference current

consumption

µA

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