ATmega162 datasheet(51/324 Pages) ATMEL

51 / 324 page

2513K–AVR–07/09

ATmega162/V

Figure 25. Brown-out Reset During Operation

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT. Refer to

page 52 for details on operation of the Watchdog Timer.

Figure 26. Watchdog Reset During Operation

MCU Control and

Status Register –

MCUCSR

The MCU Control and Status Register provides information on which reset source caused an

MCU Reset.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

VCC

RESET

TIME-OUT

INTERNAL

RESET

VBOT-

VBOT+

tTOUT

Bit

765

432

JTD

–

SM2

JTRF

WDRF

BORF

EXTRF

PORF

MCUCSR

Read/Write

R/W

Initial Value

See Bit Description

ATmega162 데이터시트(PDF) 51 Page - ATMEL Corporation

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