ATmega162 datasheet(94/324 Pages) ATMEL

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2513K–AVR–07/09

ATmega162/V

The design of the output compare pin logic allows initialization of the OC0 state before the out-

put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of

operation. See “8-bit Timer/Counter Register Description” on page 100.

Compare Output Mode

and Waveform

Generation

The Waveform Generator uses the COM01:0 bits differently in Normal, CTC, and PWM modes.

For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no action on the OC0

non-PWM modes refer to Table 48 on page 101. For fast PWM mode, refer to Table 49 on page

101, and for phase correct PWM refer to Table 50 on page 101.

A change of the COM01:0 bits state will have effect at the first Compare Match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0 strobe bits.

Modes of

Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output

mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM01:0 bits control whether the output should be set, cleared, or toggled at a Compare

Match (See “Compare Match Output Unit” on page 93.).

For detailed timing information refer to Figure 40, Figure 41, Figure 42 and Figure 43 in

“Timer/Counter Timing Diagrams” on page 98.

Normal Mode

The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The output compare unit can be used to generate interrupts at some given time. Using the out-

put compare to generate waveforms in Normal mode is not recommended, since this will occupy

too much of the CPU time.

Clear Timer on

Compare Match (CTC)

Mode

In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manip-

ulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value

(TCNT0) matches the OCR0. The OCR0 defines the top value for the counter, hence also its

resolution. This mode allows greater control of the Compare Match output frequency. It also sim-

plifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 37. The counter value (TCNT0)

increases until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0)

is cleared.

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