ATmega162 datasheet(126/324 Pages) ATMEL

126 / 324 page

126

2513K–AVR–07/09

ATmega162/V

Timer/Counter

Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

Tn) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for

modes utilizing double buffering). Figure 55 shows a timing diagram for the setting of OCFnx.

Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling

Figure 56 shows the same timing data, but with the prescaler enabled.

Figure 56. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f

clk_I/O/8)

Figure 57 shows the count sequence close to TOP in various modes. When using phase and

frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams

will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.

The same renaming applies for modes that set the TOVn Flag at BOTTOM.

clk

(clk

I/O/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

clk

I/O

clk

(clk

I/O/8)

ATmega162 데이터시트(PDF) 126 Page - ATMEL Corporation

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