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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATmega162 데이터시트(PDF) 210 Page - ATMEL Corporation |
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ATmega162 데이터시트(HTML) 210 Page - ATMEL Corporation |
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210 / 324 page  210 2513K–AVR–07/09 ATmega162/V Figure 88. General Port Pin Schematic Diagram Scanning the RESET pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for high voltage parallel programming. An observe-only cell as shown in Figure 89 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV. Figure 89. Observe-only Cell CLK RPx RRx WRx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE CLK : I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q Q D Q Q D CLR PORTxn Q Q D CLR DDxn PINxn SLEEP SLEEP: SLEEP CONTROL Pxn I/O I/O See Boundary-Scan Description for Details! PUExn OCxn ODxn IDxn PUExn: PULLUP ENABLE for pin Pxn OCxn: OUTPUT CONTROL for pin Pxn ODxn: OUTPUT DATA to pin Pxn IDxn: INPUT DATA from pin Pxn 0 1 DQ From Previous Cell ClockDR ShiftDR To Next Cell From System Pin To System Logic FF1 |
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