MAXQ3181-RAN+ datasheet(74/84 Pages) MAXIM

74 / 84 page

Low-Power, Active Energy, Polyphase AFE

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ADC Settling Time (R_ADCACQ) (0x050)

This register is a mirror of a CPU register in the MAXQ3181. This register should not be modified by supervisory

code. This register specifies the time, in CPU clocks, that the ADC must wait after switching analog mux inputs

before beginning its conversion. This register defaults to 0x2F (47 decimal), which specifies a 48 CPU clock-cycle

delay from analog mux switching to the start of conversion.

SPI Configuration (R_SPICF) (0x052)

This register is a mirror of a CPU register in the MAXQ3181. This register configures the SPI port of the MAXQ3181.

Bit:

Name:

ADC Settling Time High Byte

Reset:

—

Bit:

Name:

ADC Settling Time Low Byte

Reset:

—

0x2F

Bit:

Name:

ESPII

SAS

—

CHR

CKPHA

CKPOL

Reset:

BIT

NAME

FUNCTION

ESPII

Enable SPI Interrupt. If set, arrival of a character on the SPI bus causes a CPU interrupt.

SAS

SPI Slave Select Polarity. If clear, SSEL is assumed to be active low; if set, SSEL is assumed to be

active high.

5:3

—

Reserved.

CHR

SPI Character Length. If clear, characters on the SPI bus are assumed to be 8 bits; if set, characters on

the SPI bus are assumed to be 16 bits.

CKPHA

SPI Clock Phase. If clear, data is sampled on the leading edge of the clock (low-to-high if the clock is

active high, and high-to-low if the clock is active low). If set, data is sampled on the trailing edge of the

clock (high-to-low if the clock is active high, and low-to-high if the clock is active low).

CKPOL

SPI Clock Polarity. If clear, the clock is assumed to be active high; if set, the clock is assumed to be

active low.

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